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| a FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR and IMD: 78 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation Power Dissipation: 380 mW @ 5 V Power-Down Mode: 50 mW @ 5 V 48-Lead LQFP APPLICATIONS Communications Base Stations Digital Synthesis Quadrature Modulation PRODUCT DESCRIPTION 10-Bit, 125 MSPS Dual TxDAC+(R) D/A Converter AD9763* FUNCTIONAL BLOCK DIAGRAM DVDD DCOM AVDD ACOM CLK1 "1" DAC IOUTA1 IOUTB1 REFIO FSADJ1 FSADJ2 GAINCTRL SLEEP IOUTA2 IOUTB2 PORT1 "1" LATCH WRT1 WRT2 REFERENCE DIGITAL INTERFACE AD9763 BIAS GENERATOR PORT2 "2" LATCH MODE "2" DAC CLK2 The AD9763 is a dual port, high speed, two-channel, 10-bit CMOS DAC. It integrates two high quality 10-bit TxDAC+ cores, a voltage reference and digital interface circuitry into a small 48-lead LQFP package. The AD9763 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9763 has been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the AD9763 to interface to two separate data ports, or to a single interleaved high speed data port. In interleaving mode the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor.** The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides differential current output thus supporting single-ended or differential applications. Both DACs can be simultaneously updated and provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%. The AD9763 is manufactured on an advanced low cost CMOS process. It operates from a single supply of 3.0 V to 5.0 V and consumes 380 mW of power. PRODUCT HIGHLIGHTS 1. The AD9763 is a member of a pin-compatible family of dual TxDACs providing 8-, 10-, 12- and 14-bit resolution. 2. Dual 10-Bit, 125 MSPS DACs: A pair of high performance DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 3. Matching: Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. 4. Low Power: Complete CMOS Dual DAC function operates on 380 mW from a 3.0 V to 5.0 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-Chip Voltage Reference: The AD9763 includes a 1.20 V temperature-compensated bandgap voltage reference. 6. Dual 10-Bit Inputs: The AD9763 features a flexible dualport interface allowing dual or interleaved input data. TxDAC+ is a registered trademark of Analog Devices, Inc. **Patent pending. **Please see GAINCTRL Mode section, for important date code information on this feature. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 AD9763-SPECIFICATIONS DC SPECIFICATIONS (T Parameter RESOLUTION DC ACCURACY1 Integral Linearity Error (INL) Differential Linearity Error (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Gain Match Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Digital Supply Current (IDVDD)5 Supply Current Sleep Mode (IAVDD) Power Dissipation4 (5 V, IOUTFS = 20 mA) Power Dissipation5 (5 V, IOUTFS = 20 mA) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Supply Rejection Ratio7--AVDD Power Supply Rejection Ratio7--DVDD OPERATING RANGE MIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted.) Min 10 -1 -0.5 -0.02 -2 -5 -1.6 -0.14 2.0 -1.0 0.1 0.07 +1 +0.5 +0.02 +2 +5 +1.6 +0.14 20.0 +1.25 Typ Max Units Bits LSB LSB % of FSR % of FSR % of FSR % of FSR dB mA V k pF V nA V M MHz ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C 0.25 1 0.1 100 5 1.14 1.20 100 1.26 0.1 1 0.5 0 50 100 50 1.25 3 2.7 5 5 71 5 8 380 420 450 5.5 5.5 75 7 15 12.0 410 450 +0.4 +0.025 +85 -0.4 -0.025 -40 V V mA mA mA mA mW mW mW % of FSR/V % of FSR/V C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz. 5 Measured at fCLOCK = 100 MSPS and f OUT = 1 MHz. 6 Measured as unbuffered voltage output with I OUTFS = 20 mA and 50 RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and f OUT = 40 MHz. 7 10% Power supply variation. Specifications subject to change without notice. -2- REV. B AD9763 DYNAMIC SPECIFICATIONS (T Output, 50 Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (90% to 10%)1 Output Noise (IOUTFS = 20 mA) Output Noise (IOUTFS = 2 mA) AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 100 MSPS; fOUT = 1.00 MHz 0 dBFS Output -6 dBFS Output -12 dBFS Output -18 dBFS Output fCLOCK = 65 MSPS; fOUT = 1.00 MHz fCLOCK = 65 MSPS; fOUT = 2.51 MHz fCLOCK = 65 MSPS; fOUT = 5.02 MHz fCLOCK = 65 MSPS; fOUT = 14.02 MHz fCLOCK = 65 MSPS; fOUT = 25 MHz fCLOCK = 125 MSPS; fOUT = 25 MHz fCLOCK = 125 MSPS; fOUT = 40 MHz Spurious-Free Dynamic Range Within a Window fCLOCK = 100 MSPS; fOUT = 1.00 MHz; 2 MHz Span fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 10 MHz Span fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 10 MHz Span fCLOCK = 125 MSPS; fOUT = 5.04 MHz; 10 MHz Span Total Harmonic Distortion fCLOCK = 100 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.00 MHz fCLOCK = 125 MSPS; fOUT = 4.00 MHz fCLOCK = 125 MSPS; fOUT = 10.00 MHz Multitone Power Ratio (Eight Tones at 110 kHz Spacing) fCLOCK = 65 MSPS; fOUT = 2.00 MHz to 2.99 MHz 0 dBFS Output -6 dBFS Output -12 dBFS Output -18 dBFS Output Channel Isolation fCLOCK = 125 MSPS; fOUT = 10 MHz fCLOCK = 125 MSPS; fOUT = 40 MHz NOTES 1 Measured single-ended into 50 load. Specifications subject to change without notice. MIN to TMAX, AVDD = +5 V, DVDD = +5 V, I OUTFS = 20 mA, Differential Transformer Coupled Doubly Terminated, unless otherwise noted) Min 125 Typ Max Units MSPS ns ns pV-s ns ns pA/Hz pA/Hz 35 1 5 2.5 2.5 50 30 69 78 74 69 61 79 78 75 66 55 67 60 85 80 82 82 -77 -77 -74 -72 -69 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 78 76 74 71 67 85 77 dBc dBc dBc dBc dBc dBc REV. B -3- AD9763-SPECIFICATIONS DIGITAL SPECIFICATIONS (T Parameter DIGITAL INPUTS Logic "1" Voltage @ DVDD = +5 V Logic "1" @ DVDD = 3 Logic "0" Voltage @ DVDD = +5 V Logic "0" @ DVDD = 3 Logic "1" Current Logic "0" Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW, tCPW) Specifications subject to change without notice. MIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted.) Min 3.5 2.1 0 -10 -10 5 2.0 1.5 3.5 Typ 5 3 0 Max Units V V V V A A pF ns ns ns 1.3 0.9 +10 +10 ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD ACOM AVDD MODE, CLK1, CLK2, WRT1, WRT2 Digital Inputs IOUTA1/IOUTA2, IOUTB1/IOUTB2 REFIO, FSADJ1, FSADJ2 GAINCTRL, SLEEP Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM ACOM Min -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -1.0 -0.3 -0.3 -65 Max +6.5 +6.5 +0.3 +6.5 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 +300 Units V V V V V V V V V C C C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE tS tH Model AD9763AST AD9763-EB Temperature Range -40C to +85C Package Description Package Option* DATA IN 48-Lead LQFP ST-48 Evaluation Board (WRT2) (WRT1 / IQWRT) (CLK2) (CLK1/ IQCLK) t LPW t CPW *ST = Thin Plastic Quad Flatpack. THERMAL CHARACTERISTICS Thermal Resistance IOUTA OR IOUTB t PD 48-Lead LQFP JA = 91C/W Figure 1. Timing Diagram for Dual and Interleaved Modes See Dynamic and Digital Sections for timing specifications. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9763 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. B AD9763 PIN FUNCTION DESCRIPTIONS Pin No. 1-10 11-14, 33-36 15, 21 16, 22 17 18 19 20 23-32 37 38 39, 40 41 42 43 44 45, 46 47 48 Name PORT1 NC DCOM1, DCOM2 DVDD1, DVDD2 WRT1/IQWRT CLK1/IQCLK CLK2/IQRESET WRT2/IQSEL PORT2 SLEEP ACOM IOUTA2, IOUTB2 FSADJ2 GAINCTRL REFIO FSADJ1 IOUTB1, IOUTA1 AVDD MODE Description Data Bits DB9-P1 to DB0-P1. No Connection. Digital Common. Digital Supply Voltage. Input write signal for PORT 1 (IQWRT in interleaving mode). Clock input for DAC1 (IQCLK in interleaving mode). Clock input for DAC2 (IQRESET in interleaving mode). Input write signal for PORT 2 (IQSEL in interleaving mode). Data Bits DB9-P2 to DB0-P2. Power-Down Control Input. Analog Common. "PORT 2" differential DAC current outputs. Full-scale current output adjust for DAC2. GAINCTRL Mode (0 = 2 resistor, 1 = 1 resistor.) Reference Input/Output. Full-scale current output adjust for DAC1. "PORT 1" differential DAC current outputs. Analog Supply Voltage. Mode Select (1 = Dual Port, 0 = Interleaved). PIN CONFIGURATION GAINCTRL FSADJ1 FSADJ2 48 47 46 45 44 43 42 41 40 39 38 37 DB9-P1 (MSB) 1 DB8-P1 2 DB7-P1 3 DB6-P1 4 DB5-P1 5 DB4-P1 6 DB3-P1 7 DB2-P1 8 DB1-P1 9 DB0-P1 10 NC 11 NC 12 SLEEP 36 NC 35 NC 34 NC 33 NC 32 DB0-P2 31 DB1-P2 30 DB2-P2 29 DB3-P2 28 DB4-P2 27 DB5-P2 26 DB6-P2 25 DB7-P2 IOUTA1 IOUTB1 IOUTB2 DCOM2 IOUTA2 DVDD2 REFIO PIN 1 IDENTIFIER AD9763 TOP VIEW (Not to Scale) 13 14 15 16 17 18 19 20 21 22 23 24 NC NC DCOM1 DVDD1 ACOM DB9-P2 (MSB) MODE AVDD WRT1/IQWRT CLK1/IQCLK NC = NO CONNECT REV. B -5- CLK2/IQRESET WRT2/IQSEL DB8-P2 AD9763 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Temperature Drift Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or DNL) Temperature drift is specified as the maximum change from the ambient (+25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. Power Supply Rejection DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. 5V THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). CLK1/IQCLK CLK2/IQRESET AVDD FSADJ1 RSET1 2k 0.1 F FSADJ2 RSET2 2k 1.2V REF PMOS CURRENT SOURCE ARRAY REFIO PMOS CURRENT SOURCE ARRAY CLK DIVIDER IOUTA1 SEGMENTED LSB SWITCHES FOR SWITCH IOUTB1 DAC1 IOUTA2 SEGMENTED LSB SWITCHES FOR SWITCH IOUTB2 DAC2 MODE DVDD GAINCTRL WRT1/ IQWRT CHANNEL 1 LATCH DB0 - DB9 DVDD DCOM *RETIMED CLOCK OUTPUT LECROY 9210 PULSE GENERATOR 50 DIGITAL DATA TEKTRONIX AWG-2021 w/OPTION 4 *AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK CHANNEL 2 LATCH ACOM DCOM DB0 - DB9 WRT2/ IQSEL 5V 50 50 SLEEP MINI CIRCUITS T1-1T TO HP3589A SPECTRUM/ NETWORK ANALYZER DAC 1 LATCH DAC 2 LATCH AD9763 MULTIPLEXING LOGIC Figure 2. Basic AC Characterization Test Setup for AD9763, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2 -6- REV. B AD9763 Typical Characterization Curves (AVDD = +5 V, DVDD = +3.3 V, IOUTFS = 20 mA, 50 otherwise noted.) Doubly Terminated Load, Differential Output, TA = +25 C, SFDR up to Nyquist, unless 90 80 0dBFS 80 0dBFS 75 80 5MSPS SFDR - dBc SFDR - dBc 25MSPS 70 SFDR - dBc 75 -6dBFS -6dBFS 70 -12dBFS 65 65MSPS 60 125MSPS 50 1 10 fOUT - MHz 100 70 -12dBFS 65 0.00 0.50 1.00 1.50 fOUT - MHz 2.00 2.50 60 0 2 4 8 6 fOUT - MHz 10 12 Figure 3. SFDR vs. fOUT @ 0 dBFS Figure 4. SFDR vs. fOUT @ 5 MSPS Figure 5. SFDR vs. fOUT @ 25 MSPS 80 0dBFS 75 -6dBFS 70 80 0dBFS 75 70 80 IOUTFS = 20mA 75 70 65 60 55 50 0 5 10 15 20 fOUT - MHz 25 30 35 IOUTFS = 5mA SFDR - dBc SFDR - dBc -12dBFS 65 65 60 55 50 0 -12dBFS SFDR - dBc -6dBFS IOUTFS = 10mA 60 55 50 0 5 10 15 20 fOUT - MHz 25 30 35 10 20 30 40 fOUT - MHz 50 60 70 Figure 6. SFDR vs. fOUT @ 65 MSPS Figure 7. SFDR vs. fOUT @ 125 MSPS Figure 8. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS 85 910kHz/10MSPS 80 85 5MHz/25MSPS 80 1MHz/5MSPS 80 3.38/3.36MHz@25MSPS 0.965/1.035MHz@7MSPS 75 6.75/7.25MHz@65MSPS 2.27MHz/25MSPS SFDR - dBc SFDR - dBc SFDR - dBc 13MHz/65MSPS 25MHz/125MSPS 75 70 65 60 55 -20 75 2MHz/10MSPS 70 70 65 65 5.91MHz/65MSPS 11.37MHz/125MSPS 60 55 -20 60 16.9/18.1MHz@125MSPS 0 -16 -8 -12 AOUT - dBFS -4 0 -16 -12 -8 AOUT - dBFS -4 55 -20 -16 -12 -8 AOUT - dBFS -4 0 Figure 9. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/11 Figure 10. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5 Figure 11. Dual-Tone SFDR vs. AOUT @ fOUT = fCLOCK/7 REV. B -7- AD9763 70 0.25 0.20 0.15 0.30 0.25 0.20 0.10 IOUTFS = 20mA SINAD - dBc 65 IOUTFS = 10mA INL - LSBs 0.05 0 -0.05 -0.10 -0.15 DNL - LSBs 0 200 400 600 CODE 800 1000 0.15 0.10 0.05 0 -0.05 -0.01 0 200 400 600 CODE 800 1000 60 IOUTFS = 5mA 55 20 -0.20 40 60 80 100 fCLOCK - MSPS 120 140 -0.25 Figure 12. SINAD vs. fCLOCK and IOUTFS @ fOUT = 5 MHz and 0 dBFS Figure 13. Typical INL Figure 14. Typical DNL 85 80 75 fOUT = 1MHz 0.05 GAIN ERROR 1.0 10 0 GAIN ERROR - % FS fOUT = 10MHz OFFSET ERROR - % FS -10 0.03 OFFSET ERROR 0.5 -20 -30 SFDR - dBc 70 65 60 55 50 fOUT = 60MHz 80 100 fOUT = 25MHz dBm 0.00 0.00 -40 -50 -60 -70 -80 fOUT = 40MHz -0.03 -0.5 45 0 20 40 60 -60 -40 -20 TEMPERATURE - C -0.05 -40 -20 0 20 40 60 TEMPERATURE - C 80 -1.0 -90 0 10 30 20 FREQUENCY - MHz 40 Figure 15. SFDR vs. Temperature @ 125 MSPS, 0 dBFS Figure 16. Reference Voltage Drift vs. Temperature Figure 17. Single-Tone SFDR @ fCLK = 125 MSPS 0 -10 -20 -30 dBm dBm 0 -10 -20 -30 -40 -50 -60 -70 -80 0 -90 20 10 30 FREQUENCY - MHz 40 0 20 10 30 FREQUENCY - MHz 40 -40 -50 -60 -70 -80 -90 Figure 18. Dual-Tone SFDR @ fCLK = 125 MSPS Figure 19. Four-Tone SFDR @ fCLK = 125 MSPS -8- REV. B AD9763 5V CLK1/IQCLK AVDD RSET1 2k IREF1 0.1 F FSADJ1 REFIO CLK DIVIDER CLK2/IQRESET SLEEP ACOM IOUTA1 SEGMENTED LSB I SWITCHES FOR SWITCH OUTB1 DAC1 IOUTA2 SEGMENTED LSB SWITCHES FOR SWITCH IOUTB2 DAC2 MODE DVDD DCOM WRT1/ IQWRT DB0 - DB9 DB0 - DB9 DIGITAL DATA INPUTS WRT2/ IQSEL 5V VOUT 2A VOUT 2B RL2B 50 RL2A 50 VDIFF = VOUT A - VOUT B VOUT 1A VOUT 1B RL1B 50 RL1A 50 PMOS CURRENT SOURCE ARRAY PMOS CURRENT SOURCE ARRAY DAC 1 LATCH RSET2 2k IREF 2 FSADJ2 DAC 2 LATCH 1.2V REF GAINCTRL AD9763 MULTIPLEXING LOGIC CHANNEL 1 LATCH CHANNEL 2 LATCH Figure 20. Simplified Block Diagram REFERENCE OPERATION FUNCTIONAL DESCRIPTION Figure 20 shows a simplified block diagram of the AD9763. The AD9763 consists of two DACs, each one with its own independent digital control logic and full-scale output current control. Each DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (IOUTFS). The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSB is a binary weighted fraction of the middle bit current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances the dynamic performance for multitone or low amplitude signals and helps maintain the DAC's high output impedance (i.e., >100 k). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital sections of the AD9763 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 3 V to 5.5 V range. The digital section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap voltage reference and two reference control amplifiers. The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the Full Scale Adjust (FSADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is 32 x IREF. The AD9763 contains an internal 1.20 V bandgap reference. This can easily be overridden by an external reference with no effect on performance. REFIO serves as either an input or output, depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 F capacitor. The internal reference voltage will be present at REFIO. If the voltage at REFIO is to be used elsewhere in the circuit, an external buffer amplifier with an input bias current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 21. OPTIONAL EXTERNAL REFERENCE BUFFER GAINCTRL +1.2V REF REFIO 0.1 F IREF 2k FSADJ AVDD AD9763 REFERENCE SECTION CURRENT SOURCE ARRAY ACOM ADDITIONAL EXTERNAL LOAD Figure 21. Internal Reference Configuration An external reference can be applied to REFIO as shown in Figure 22. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 F compensation capacitor is not required since the internal reference is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. GAINCTRL AVDD +1.2V REF REFIO FSADJ IREF 2k AVDD AD9763 REFERENCE SECTION CURRENT SOURCE ARRAY ACOM EXTERNAL REFERENCE Figure 22. External Reference Configuration REV. B -9- AD9763 GAINCTRL MODE The AD9763 allows the gain of each channel to be independently set by connecting one RSET resistor to FSADJ1 and another RSET resistor to FSADJ2. To add flexibility and reduce system cost, a single RSET resistor can be used to set the gain of both channels simultaneously. When GAINCTRL is low (i.e., connected to AGND), the independent channel gain control mode using two resistors is enabled. In this mode, individual RSET resistors should be connected to FSADJ1 and FSADJ2. When GAINCTRL is high (i.e., connected to AVDD), the master/slave channel gain control mode using one resistor is enabled. In this mode, a single RSET resistor is connected to FSADJ1 and the resistor on FSADJ2 must be removed. NOTE: Only parts with date code of 9930 or later have the Master/Slave GAINCTRL function. For parts with a date code before 9930, Pin 42 must be connected to AGND, and the part will operate in the two resistor, independent gain control mode. REFERENCE CONTROL AMPLIFIER The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note, RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 or 75 cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply: VOUTA = IOUTA x RLOAD VOUTB = IOUTB x RLOAD (5) (6) Note the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. VDIFF = (IOUTA - IOUTB) x RLOAD (7) Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be expressed as: VDIFF = {(2 x DAC CODE - 1023)/1024} x (32 x RLOAD/RSET) x VREFIO (8) Both of the DACs in the AD9763 contain a control amplifier that is used to regulate the full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter as shown in Figure 21, so that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scale factor to set IOUTFS as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 A and 625 A. The wide adjustment range of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9763, which is proportional to IOUTFS (refer to the Power Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency, small signal multiplying applications. DAC TRANSFER FUNCTION These last two equations highlight some of the advantages of operating the AD9763 differentially. First, the differential operation will help cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion and dc offsets. Second, the differential code-dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. Note, the gain drift temperature performance for a single-ended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9763 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship as shown in Equation 8. ANALOG OUTPUTS Both DACs in the AD9763 provide complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023) while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as: IOUTA = (DAC CODE /1024) x IOUTFS IOUTB = (1023 - DAC CODE)/1024) x IOUTFS (1) (2) The complementary current outputs in each DAC, IOUTA and IOUTB, may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9763 is optimum and specified using a differential transformer coupled output in which the voltage swing at IOUTA and IOUTB is limited to 0.5 V. If a single-ended unipolar output is desirable, IOUTA should be selected. The distortion and noise performance of the AD9763 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. This is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough and noise. where DAC CODE = 0 to 1023 (i.e., Decimal Representation). As previously mentioned, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage, VREFIO and external resistor RSET. It can be expressed as: IOUTFS = 32 x IREF where IREF = VREFIO /RSET (4) (3) -10- REV. B AD9763 Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9763 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 k in parallel with 5 pF. It is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration will result in the optimum dc linearity. Note the INL/DNL specifications for the AD9763 are measured with IOUTA maintained at a virtual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of -1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9763. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. Applications requiring the AD9763's output (i.e., VOUTA and/or VOUTB) to extend its output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect the AD9763's linearity performance and subsequently degrade its distortion performance. DIGITAL INPUTS DAC TIMING The AD9763 can operate in two timing modes, dual and interleaved, which are described below. The block diagram in Figure 25 represents the latch architecture in the interleaved timing mode. DUAL PORT MODE TIMING For the following section, refer to Figure 2. When the MODE pin is at Logic 1, the AD9763 operates in dual port mode. The AD9763 functions as two distinct DACs. Each DAC has its own completely independent digital input and control lines. The AD9763 features a double buffered data path. Data enters the device through the channel input latches. This data is then transferred to the DAC latch in each signal path. Once the data is loaded into the DAC latch, the analog output will settle to its new value. For general consideration, the WRT lines control the channel input latches and the CLK lines control the DAC latches. Both sets of latches are updated on the rising edge of their respective control signals. The rising edge of CLK should occur before or simultaneously with the rising edge of WRT. Should the rising edge of CLK occur after the rising edge of WRT, a 2 ns minimum delay should be maintained from the rising edge of WRT to the rising edge of CLK. Timing specifications for dual port mode are given in Figures 23 and 24. tS DATA IN tH WRT1/WRT2 CLK1/CLK2 t LPW t CPW The AD9763's digital inputs consist of two independent channels. For the dual port mode, each DAC has its own dedicated 10-bit data port, WRT line and CLK line. In the interleaved timing mode, the function of the digital control pins changes as described in the Interleaved Mode Timing section. The 10-bit parallel data inputs follow straight binary coding where DB9 is the Most Significant Bit (MSB) and DB0 is the Least Significant Bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. The digital interface is implemented using an edge-triggered master slave latch. The DAC outputs are updated following either the rising edge, or every other rising edge of the clock, depending on whether dual or interleaved mode is being used. The DAC outputs are designed to support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. IOUTA OR IOUTB t PD Figure 23. Dual Mode Timing DATAIN D1 D2 D3 D4 D5 WRT1/WRT2 CLK1/CLK2 IOUTA OR IOUTB xx D1 D2 D3 D4 Figure 24. Dual Mode Timing REV. B -11- AD9763 INTERLEAVED MODE TIMING For the following section, refer to Figure 25. When the MODE pin is at Logic 0, the AD9763 operates in interleaved mode. WRT1 now functions as IQWRT and CLK1 functions as IQCLK. WRT2 functions as IQSEL and CLK2 functions as IQRESET. Data enters the device on the rising edge of IQWRT. The logic level of IQSEL will steer the data to either Channel Latch 1 (IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). When IQRESET is high, IQCLK is disabled. When IQRESET goes low, the following rising edge on IQCLK will update both DAC latches with the data present at their inputs. In the interleaved mode, IQCLK is divided by 2 internally. Following this first rising edge, the DAC latches will only be updated on every other rising edge of IQCLK. In this way, IQRESET can be used to synchronize the routing of the data to the DACs. As with the dual port mode, IQCLK should occur before or simultaneously with IQWRT. INTERLEAVED DATA (WRT2) IQSEL xx D1 D2 D3 D4 D5 (WRT1) IQWRT (CLK1) IQCLK (EXTERNAL) IQCLK 2 (EXTERNAL) (CLK2) IQRESET DAC OUTPUT PORT 1 DAC OUTPUT PORT 2 xx D1 D3 D4 D2 xx Figure 27. Interleaved Mode Timing INTERLEAVED DATA IN, PORT 1 PORT 1 INPUT LATCH DAC1 LATCH DAC1 IQWRT IQSEL PORT 2 INPUT LATCH IQCLK IQRESET DEINTERLEAVED DATA OUT DAC2 LATCH DAC2 2 The internal digital circuitry of the AD9763 is capable of operating over a digital supply range of 3 V to 5.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage of the TTL drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure proper compatibility with most TTL logic families. Figure 28 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the AD9763 remains enabled if this input is left disconnected. Since the AD9763 is capable of being clocked up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9763 with reduced logic swings and a corresponding digital supply (DVDD) will result in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9763 as well as its required min/max input logic level thresholds. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20 to 100 ) between the AD9763 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. For longer board traces and high data update rates, stripline techniques with proper impedance and termination resistors should be considered to maintain "clean" digital inputs. The external clock driver circuitry should provide the AD9763 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform. Thus, the clock input should be driven by the fastest logic family suitable for the application. Figure 25. Latch Structure Interleaved Mode Timing specifications for interleaved mode are given in Figures 26 and 27. The digital inputs are CMOS-compatible with logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (DVDD) or VTHRESHOLD = DVDD/2 ( 20%) tS DATA IN tH IQWRT IQCLK t LPW t CPW IOUTA OR IOUTB t PD Figure 26. Interleaved Mode Timing -12- REV. B AD9763 Note that the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., DVDD/2) and meets the min/max logic threshold. This will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. Also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and, subsequently, cut into the required data setup and hold times. DVDD Logic Level "1" to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 x AVDD. This digital input also contains an active pull-down circuit that ensures the AD9763 remains enabled if this input is left disconnected. The AD9763 takes less than 50 ns to power down and approximately 5 s to power back up. POWER DISSIPATION DIGITAL INPUT The power dissipation, PD, of the AD9763 is dependent on several factors that include: (1) The power supply voltages (AVDD and DVDD), (2) the full-scale current output IOUTFS, (3) the update rate fCLOCK, (4) and the reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. I AVDD is directly proportional to IOUTFS as shown in Figure 30 and is insensitive to fCLOCK. 80 Figure 28. Equivalent Digital Input INPUT CLOCK AND DATA TIMING RELATIONSHIP 70 60 50 40 30 20 10 SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9763 is rising edge triggered, and so exhibits SNR sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9763 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 29 shows the relationship of SNR to clock placement with different sample rates. Note that at the lower sample rates, much more tolerance is allowed in clock placement, while much more care must be taken at higher rates. 70 IAVDD 0 5 10 IOUTFS 15 20 25 Figure 30. IAVDD vs. IOUTFS 60 50 SNR - dBc 40 30 Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 31 and 32 show IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 5 V and DVDD = 3 V, respectively. Note how IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3 V. 35 30 25 IDVDD - mA 20 125MSPS 10 0 -4 100MSPS 20 65MSPS 15 10 5 -3 -2 -1 0 1 2 3 4 TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE - ns Figure 29. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS SLEEP MODE OPERATION 25MSPS 5MSPS The AD9763 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 3.0 V to 5.5 V and temperature range. This mode can be activated by applying a 0 0 0.10 0.20 0.30 RATIO - fOUT/fCLK 0.40 0.50 Figure 31. IDVDD vs. Ratio @ DVDD = 5 V REV. B -13- AD9763 18 16 14 100MSPS 12 IDVDD - mA AD9763 125MSPS IOUTA MINI-CIRCUITS T1-1T RLOAD IOUTB 10 65MSPS 8 6 25MSPS 4 2 0 5MSPS OPTIONAL RDIFF Figure 33. Differential Output Using a Transformer 0 0.10 0.20 0.30 RATIO - fOUT/fCLK 0.40 0.50 Figure 32. IDVDD vs. Ratio @ DVDD = 3 V APPLYING THE AD9763 Output Configurations The following sections illustrate some typical output configurations for the AD9763. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level-shifting, within the bandwidth of the chosen op amp. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriatelysized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. Note that IOUTA provides slightly better performance than IOUTB. DIFFERENTIAL COUPLING USING A TRANSFORMER The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9763. A differential resistor, RDIFF, may be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 34. The AD9763 is configured with two equal load resistors, RLOAD, of 25 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amps distortion performance by preventing the DACs high slewing output from overloading the op amp's input. The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate from a dual supply since its output is approximately 1.0 V. A high speed amplifier capable of preserving the differential performance of the AD9763, while meeting other system level objectives (i.e., cost, power), should be selected. The op amp's differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. 500 An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 33. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's passband. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. AD9763 IOUTA 225 225 IOUTB COPT 500 25 25 AD8047 Figure 34. DC Differential Coupling Using an Op Amp -14- REV. B AD9763 The differential circuit shown in Figure 35 provides the necessary level-shifting required in a single supply system. In this case AVDD, which is the positive analog supply for both the AD9763 and the op amp, is also used to level-shift the differential output of the AD9763 to midsupply (i.e., AVDD/2). The AD8055 is a suitable op amp for this application. 500 COPT RFB 200 AD9763 IOUTA IOUTFS = 10mA U1 IOUTB 200 VOUT = IOUTFS RFB AD9763 IOUTA 225 225 IOUTB COPT 25 25 500 AD8055 1k AVDD Figure 37. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Figure 35. Single Supply DC Differential Coupled Circuit SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT Figure 36 shows the AD9763 configured to provide a unipolar output range of approximately 0 V to +0.5 V for a doubly terminated 50 cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 . In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL) as discussed in the Analog Output section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. AD9763 IOUTA 50 IOUTB 25 50 Many applications seek high speed and high performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement and routing, as well as power supply bypassing and grounding to ensure optimum performance. Figures 44 to 51 illustrate the recommended printed circuit board ground, power and signal plane layouts which are implemented on the AD9763 evaluation board. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the Power Supply Rejection Ratio. For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC's full-scale current, IOUTFS. AC noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. The PSRR vs. frequency of the AD9763 AVDD supply over this frequency range is shown in Figure 38. 90 IOUTFS = 20mA VOUTA = 0 TO +0.5V 85 PSRR - dB Figure 36. 0 V to 0.5 V Unbuffered Voltage Output SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION 80 Figure 37 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9763 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, thus minimizing the nonlinear output impedance effect on the DAC's INL performance as discussed in the Analog Output section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1's slewing capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1's voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since the signal current U1 will be required to sink will be subsequently reduced. 75 70 0.20 0.30 0.40 0.50 0.60 0.70 0.80 FREQUENCY - MHz 0.90 1.00 1.10 Figure 38. Power Supply Rejection Ratio of AD9763 Note that the units in Figure 38 are given in units of (amps out/ volts in). Noise on the analog power supply has the effect of modulating the internal current sources, and therefore the output current. The voltage noise on AVDD, therefore, will be added in a nonlinear manner to the desired IOUT. PSRR is very code-dependent thus producing mixing effects which can modulate low frequency power supply noise to higher frequencies. REV. B -15- AD9763 Worst case PSRR for either one of the differential DAC outputs will occur when the full-scale current is directed towards that output. As a result, the PSRR measurement in Figure 38 represents a worst case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and, for simplicity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise will appear as current noise superimposed on the DAC's full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 38 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 38 by the scaling factor 20 x Log (RLOAD ). For instance, if RLOAD is 50 , the PSRR is reduced by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in Figure 38, becomes 51 dB VOUT/VIN). Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9763 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close to the chip as physically possible. For those applications that require a single +5 V or +3 V supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in Figure 39. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. FERRITE BEADS TTL/CMOS LOGIC CIRCUITS ELECTROLYTIC CERAMIC AVDD 100 F 10-22 F 0.1 F ACOM TANTALUM +5V POWER SUPPLY NYQUIST FILTERS QUADRATURE MODULATOR APPLICATIONS Using the AD9763 for Quadrature Amplitude Modulation QAM is one of the most widely used digital modulation schemes in digital communications systems. This modulation technique can be found in FDM as well as spread spectrum (i.e., CDMA) based systems. A QAM signal is a carrier frequency that is modulated in both amplitude (i.e., AM modulation) and phase (i.e., PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90 phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. A common and traditional implementation of a QAM modulator is shown in Figure 40. The modulation is performed in the analog domain in which two DACs are used to generate the baseband I and Q components. Each component is then typically applied to a Nyquist filter before being applied to a quadrature mixer. The matching Nyquist filters shape and limit each component's spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with the in-phase and quadrature carrier frequency and then sums the two outputs to provide the QAM signal. 10 DAC DSP OR ASIC 10 DAC CARRIER FREQUENCY 0 90 TO MIXER Figure 40. Typical Analog QAM Architecture Figure 39. Differential LC Filter for Single +5 V and +3 V Applications In this implementation, it is much more difficult to maintain proper gain and phase matching between the I and Q channels. The circuit implementation shown in Figure 41 helps improve upon the matching between the I and Q channels, as well as showing a path for upconversion using the AD8346 quadrature modulator. The AD9763 provides both I and Q DACs as well as a common reference that will improve the gain matching and stability. RCAL can be used to compensate for any mismatch in gain between the two channels. The mismatch may be attributed to the mismatch between RSET1 and RSET2, effective load resistance of each channel, and/or the voltage offset of the control amplifier in each DAC. The differential voltage outputs of both DACs in the AD9763 are fed into the respective differential inputs of the AD8346 via matching networks. -16- REV. B AD9763 5V DVDD CLK1 FSADJ1 SLEEP AVDD 200 2.5k 500 CFILTER 500 200 BBIN 200 2.5k 0.1 F BBIP VPBF RSET1 3.83k IOUTFS 11mA I DATA INPUT WRT1 U1 DAC DAC LATCHES IOUTA IOUTB INPUT LATCHES + VOUT ("I DAC") AD9763 WRT2 Q DATA INPUT RSET2 3.74k FSADJ2 RCAL 200 REFIO GAINCTRL CLK2 ACOM DCOM 200 NOTE: 500 RESISTOR NETWORK - OHMTEK ORN SERIES 2.5k RESISTOR NETWORK INPUT LATCHES ("Q DAC") U2 DAC DAC LATCHES 200 QOUTA QOUTB 500 CFILTER 500 LOIPP 2.5k 500 BBQP PHASE SPLITTER LOIPN BBQN AD8346 0.1 F Figure 41. Baseband QAM Implementation Using an AD9763 and AD8346 I and Q digital data can be fed into the AD9763 in two different ways. In dual port mode, The digital I information drives one input port, while the digital Q information drives the other input port. If no interpolation filter precedes the DAC, the symbol rate will be the rate at which the system clock drives the CLK and WRT pins on the AD9763. In interleaved mode, the digital input stream at Port 1 contains the I and the Q information in alternating digital words. Using IQSEL and IQRESET, the AD9763 can be synchronized to the I and Q data stream. The internal timing of the AD9763 routes the selected I and Q data to the correct DAC output. In interleaved mode, if no interpolation filter precedes the AD9763, the symbol rate will be half that of the system clock driving the digital data stream and the IQWRT and IQCLK pins on the AD9763. CDMA interference with other signals being transmitted by air. Regulatory bodies define a spectral mask outside of the transmit band, and the ACP must fall under this mask. If distortion in the transmit path causes the ACP to be above the spectral mask, then filtering, or different component selection, is needed to meet the mask requirements. Figure 42 shows the AD9763, when used with the AD8346, reconstructing a wideband CDMA signal at 1.8 GHz. The baseband signal is being sampled at 65 MSPS and has a chip rate of 8M chips. -30 -40 -50 -60 -70 Carrier Division Multiple Access, or CDMA, is an air transmit/ receive scheme where the signal in the transmit path is modulated with a pseudorandom digital code (sometimes referred to as the spreading code). The effect of this is to spread the transmitted signal across a wide spectrum. Similar to a DMT waveform, a CDMA waveform containing multiple subscribers can be characterized as having a high peak to average ratio (i.e., crest factor), thus demanding highly linear components in the transmit signal path. The bandwidth of the spectrum is defined by the CDMA standard being used, and in operation is implemented by using a spreading code with particular characteristics. Distortion in the transmit path can lead to power being transmitted out of the defined band. The ratio of power transmitted in-band to out-of-band is often referred to as Adjacent Channel Power (ACP). This is a regulatory issue due to the possibility of == dB -80 -90 -100 -110 c11 c11 C0 cu1 C0 cu1 -120 -130 CENTER 2.4GHz 3MHz FREQUENCY SPAN 30MHz Figure 42. CDMA Signal, 8 M Chips Sampled at 65 MSPS, Recreated at 2.4 GHz, Adjacent Channel Power > 60 dBm REV. B -17- AD9763 DVDD CLK1 RSET1 2k FSADJ1 AVDD 3V U1 DAC DAC LATCHES IOUTA IOUTB 100 500 500 100 500 500 IIPP IIPN AD6122 I DATA INPUT WRT1 INPUT LATCHES ("I DAC") AD9763 WRT2 Q DATA INPUT RSET2 1.9k FSADJ2 RCAL 220 GAINCTRL REFIO SLEEP CLK2 0.1 F ACOM DCOM INPUT LATCHES ("Q DAC") U2 DAC DAC LATCHES QOUTA QOUTB 100 LOIPP LOIPN 500 500 500 100 500 IIQP IIQN 2 PHASE SPLITTER MODOPP MODOPN TEMPERATURE COMPENSATION VCC VCC REFIN GAIN CONTROL VGAIN GAIN CONTROL SCALE FACTOR TXOPP TXOPN Figure 43. CDMA Transmit Application Using AD9763 and AD6122 Figure 43 shows an example of the AD9763 used in a W-CDMA transmitter application using the AD6122 CDMA 3 V IF subsystem. The AD6122 has functions, such as external gain control and low distortion characteristics, needed for the superior Adjacent Channel Power (ACP) requirements of W-CDMA. EVALUATION BOARD General Description The AD9763-EB is an evaluation board for the AD9763 10-bit dual D/A converter. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9763 in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9763 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs can be used in dual port or interleaved mode, and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. When operating the AD9763, best performance is obtained when running the Digital Supply (DVDD) at +3 V and the Analog Supply (AVDD) at +5 V. -18- REV. B AD9763 POWER DECOUPLING AND INPUT CLOCKS B1 DVDDIN BAN-JACK B2 BAN-JACK RED TP10 L1 BEAD DVDD C9 BLK 10 F TP37 2 25V 1 B3 AVDDIN BLK TP39 RED TP11 L2 BEAD 1 2 DVDD AVDD C10 BLK 10 F TP40 25V BLK TP41 BLK TP42 1 2 BLK TP38 BAN-JACK B4 BAN-JACK C7 0.1 F 1 2 C8 0.01 F TP43 BLK DGND TP44 BLK AGND JP9 DCLKIN1 WHT TP29 DGND;3,4,5 1 2 3 AB DCLKIN2 DVDD 1 JP6 2 3 AB WRT1IN S1 IQWRT JP16 JP2 4 10 5 11 13 CLK1IN S2 IQCLK WHT TP30 DGND;3,4,5 1 JP5 A2B I C 3 PRE J PRE J JP1 3 1 2 U1 Q U2 Q Q 9 CLK K Q CLR 15 6 CLK K CLR 14 DVDD 12 7 CLK2IN S3 RESET WHT TP31 DGND;3,4,5 1 JP4 A2B I C TSSOP112 TSSOP112 3 DGND;8 DVDD;16 3 DGND;8 DVDD;16 DVDD AB 1 2 WRT2IN S4 IQSEL WHT TP32 DGND;3,4,5 1 2 1 2 1 2 1 2 1 JP3 A2B I C JP7 3 /2 CLOCK DIVIDER WRT1 CLK1 CLK2 WRT2 SLEEP R1 50 R2 50 R3 50 R4 50 WHT TP33 SLEEP 1 2 R13 50 RP16 RCOM 1 RP9 RCOM 1 R1 22 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 R1 22 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 INP1 INP2 INP3 INP4 INP5 INP6 INP7 INP8 RP10 INP9 INP10 INP11 INP12 INP13 INP14 INCK1 RP15 RCOM 1 R1 22 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 RCOM 1 R1 22 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30 INP31 INP32 INP33 INP34 INP35 INP36 INCK2 Figure 44. Power Decoupling and Clocks on AD9763 Evaluation Board REV. B -19- AD9763 DIGITAL INPUT SIGNAL CONDITIONING RP3 RCOM R1 22 1 2 3 4 5 6 7 8 9 10 1 R9 RP1 RCOM R1 22 2 3 4 5 6 7 8 9 10 R9 RP13 RCOM R1 33 1 2 3 4 5 6 7 8 9 10 R9 RP11 RCOM R1 33 1 2 3 4 5 6 7 8 9 10 R9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 1 3 5 7 9 INP1 INP2 INP3 INP4 INP5 INP6 INP7 INP8 INP9 INP10 INP11 INP12 INP13 INP14 RP5, 10 1 16 DVDD RP5, 10 2 15 DVDD DUTP1 DUTP2 DUTP3 DUTP4 DUTP5 DUTP6 DUTP7 DUTP8 DUTP9 DUTP10 DUTP11 DUTP12 DUTP13 DUTP14 RP5, 10 3 14 RP5, 10 4 13 RP5, 10 5 12 RP5, 10 6 11 P1 11 P1 13 P1 15 P1 17 P1 19 P1 21 P1 23 P1 25 P1 27 RP5, 10 7 10 RP5, 10 8 9 RP6, 10 1 16 RP6, 10 2 15 RP6, 10 3 14 RP6, 10 4 13 RP6, 10 5 12 RP6, 10 6 11 P1 29 P1 31 P1 33 P1 35 P1 37 P1 39 INCK1 RP6, 10 8 9 DCLKIN1 RP4 RCOM R1 22 1 2 3 4 5 6 7 8 9 10 R9 RP2 RCOM R1 22 1 2 3 4 5 6 7 8 9 10 R9 RP14 RCOM R1 33 1 2 3 4 5 6 7 8 9 10 R9 RP12 RCOM R1 33 1 2 3 4 5 6 7 8 9 10 R9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 1 3 5 7 9 INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30 INP31 INP32 INP33 INP34 INP35 INP36 RP7, 10 1 16 DVDD RP7, 10 2 15 DVDD DUTP23 DUTP24 DUTP25 DUTP26 DUTP27 DUTP28 DUTP29 DUTP30 DUTP31 DUTP32 DUTP33 DUTP34 DUTP35 DUTP36 RP7, 10 3 14 RP7, 10 4 13 RP7, 10 5 12 RP7, 10 6 11 P2 11 P2 13 P2 15 P2 17 P2 19 P2 21 P2 23 P2 25 P2 27 RP7, 10 7 10 RP7, 10 8 9 RP8, 10 1 16 RP8, 10 2 15 RP8, 10 3 14 RP8, 10 4 13 RP8, 10 5 12 RP8, 10 6 11 P2 29 P2 31 P2 33 P2 35 P2 37 P2 39 INCK2 RP8, 10 8 9 DCLKIN2 SPARES RP5, 10 7 10 RP8, 10 7 10 Figure 45. Digital Input Signal Conditioning -20- REV. B AD9763 DUT AND ANALOG OUTPUT SIGNAL CONDITIONING BL1 TP34 WHT DVDD 1 ACOM JP15 1 2 3 3 NC = 5 1:1 4 AGND;3,4,5 6 C1 2 VAL 1 C2 2 0.01 F 1 C3 2 0.1 F S6 OUT1 AVDD AB R11 VAL 2 1 MODE JP8 DVDD DUTP1 DUTP2 DUTP3 DUTP4 DUTP5 DUTP6 DUTP7 DUTP8 DUTP9 DUTP10 DUTP11 DUTP12 DUTP13 DUTP14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 1 2 T1 BL2 R5 50 C5 2 10pF 1 1 2 AB DB13P1MSB DB12P1 DB11P1 DB10P1 DB9P1 DB8P1 DB7P1 DB6P1 DB5P1 DB4P1 DB3P1 DB2P1 DB1P1 DB0P1 DCOM1 DVDD1 WRT1 CLK1 CLK2 WRT2 DCOM2 DVDD2 DB13P2MSB DB12P2 MODE 48 AVDD 47 R6 50 C4 2 10pF 1 TP45 WHT R9 1.92k 1 2 IA1 46 IB1 45 FSADJ1 44 REFIO 43 GAINCTRL 42 FSADJ2 41 IB2 40 C17 22nF 1 2 C16 22nF 1 2 R15 256 1 2 REFIO TP36 WHT 1 2 R14 256 1 2 C14 0.1 F R10 1.92k C15 2 SLEEP DUTP36 DUTP35 DUTP34 DUTP33 DUTP32 DUTP31 DUTP30 DUTP29 DUTP28 DUTP27 DUTP26 DUTP25 AVDD 1 3 JP10 2 U2 IA2 39 ACOM 38 SLEEP 37 DB0P2 36 DB1P2 35 DB2P2 34 DB3P2 33 DB4P2 32 DB5P2 31 C6 2 10pF 1 1 2 1 10pF 1 R7 50 1 2 R8 50 WHT TP46 BL3 TP35 WHT NC = 5 1:1 6 4 AGND;3,4,5 S11 OUT2 WRT1 CLK1 CLK2 WRT2 17 18 19 20 21 22 R12 VAL 2 1 T2 BL4 DB6P2 30 DB7P2 29 DB8P2 28 DB9P2 27 DB10P2 26 DB11P2 25 DUTP23 DUTP24 23 24 C11 21 F 1 C12 2 0.01 F 1 C13 2 0.1 F Figure 46. AD9763 and Output Signal Conditioning REV. B -21- AD9763 Figure 47. Assembly, Top Side -22- REV. B AD9763 Figure 48. Assembly, Bottom Side REV. B -23- AD9763 Figure 49. Layer 1, Top Side -24- REV. B AD9763 Figure 50. Layer 2, Ground Plane REV. B -25- AD9763 Figure 51. Layer 3, Power Plane -26- REV. B AD9763 Figure 52. Layer 4, Bottom Side REV. B -27- REV. B AD9763 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Thin Plastic Quad Flatpack (ST-48) 0.354 (9.00) BSC SQ 48 1 37 36 0.030 (0.75) 0.018 (0.45) TOP VIEW (PINS DOWN) 0.276 (7.00) BSC SQ 25 COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09) 0 MIN 12 13 24 0.019 (0.5) BSC 7 0 0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) SEATING 0.002 (0.05) PLANE -28- REV. B PRINTED IN U.S.A. C3582a-0-2/00 (rev. B) 0.063 (1.60) MAX |
Price & Availability of AD9763
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